1. Field of the Invention
The present invention relates to a semiconductor device including a circuit constituted by thin film transistors (hereinafter referred to as TFTs) and a method of manufacturing the same. For example, the present invention relates to an electro-optical device typified by a liquid crystal display panel and an electronic instrument incorporating such an electro-optical device as a part.
Note that, the xe2x80x9csemiconductor devicexe2x80x9d in the present specification indicates any device which can function by using semiconductor characteristics, and any of an electro-optical device, a semiconductor circuit and an electronic instrument is a semiconductor device.
2. Description of the Related Art
In recent years, attention has been paid to a technique for constructing a thin film transistor (TFT) by using a semiconductor thin film (thickness of about several nm to several hundreds of nm) formed on a substrate having an insulating surface. The thin film transistor is widely used for an electric device such as an IC or an electro-optical device, and particularly its development as a switching element of an image display device has been hastened. The thin film transistor includes a top gate type TFT and a bottom gate type TFT.
Since the bottom gate type TFT is little influenced by impurity diffusion from a substrate to a semiconductor layer as compared with the top gate type TFT, its reliability is high. A general structure thereof is such that an impurity region overlaps with a gate electrode.
The development of a semiconductor device including a large area integrated circuit formed of these TFTs has been advanced.
An active matrix type liquid crystal display device, an EL display device, and a direct-contact image sensor are known as its typical examples. Especially, since a TFT (hereinafter referred to as a polysilicon TFT) using a crystalline silicon film (typically a polysilicon film) as an active layer has a high field effect mobility, it is also possible to form circuits having various functions.
For example, in the active matrix type liquid crystal display device, in every function block, a pixel circuit for carrying out an image display, and a driving circuit for controlling the pixel circuit, such as a shift register circuit using a CMOS circuit as a base, a level shifter circuit, a buffer circuit, and a sampling circuit, are formed on one substrate.
In the pixel circuit of the active matrix type liquid crystal display device, a TFT (pixel TFT) is disposed in each of several tens to several millions of pixels, and a pixel electrode is provided at each of the pixel TFTs. A counter electrode is provided on a counter substrate side with a liquid crystal sandwiched therebetween, and forms a kind of capacitor using the liquid crystal as a dielectric. A voltage applied to each pixel is controlled by a switching function of the TFT, and an electric charge to the capacitor is controlled, so that the liquid crystal is driven and the amount of transmitted light is controlled to display an image.
The pixel TFT is made of an n-channel type TFT, and, as a switching element, applies the voltage to the liquid crystal to drive it. Since the liquid crystal is driven by an alternating current, a system called frame inversion driving is often adopted. In this system, in order to suppress consumed electric power to be low, it is important that characteristics required for the pixel TFT are such that an off current value (drain current flowing when the TFT is in an off operation) is made sufficiently low.
The present invention provides a technique for solving such problems, and an object of the present invention is to improve operation characteristics of a semiconductor device and to reduce consumed electric power in an electro-optical device typified by an active matrix type liquid crystal display device manufactured by using TFTs and in a semiconductor device.
Particularly, an object of the present invention is to obtain a structure of a pixel TFT (n-channel type TFT) in which an off current value is sufficiently low, and the ratio of an on current value to the off current value is high.
As shown in FIG. 1A, the present invention is characterized by including a region 102a having such a concentration gradient in an impurity region 102 that as a distance (distance in a channel length direction) from a channel formation region becomes larger, a concentration of an impurity element imparting one conductivity type is increased.
That is, the invention is characterized by including an impurity region in which as a distance from an end portion of a gate electrode 105 becomes larger toward a peripheral portion (peripheral portion in a section cut in the channel length direction) of a semiconductor layer in the channel length direction, the concentration of the impurity element (phosphorus) is gradually increased. Accordingly, in the impurity region, its electric resistance is large at the side of the channel formation region, and is low at the side of the peripheral portion of the semiconductor layer.
Further, in the present invention, since the concentration is gradually increased in the impurity region, there is no definite boundary, and in the present specification, a region in the impurity region 102 in which its impurity concentration is 1xc3x971020/cm3 or higher is called a drain region 102b. 
Further, although the drain side has been explained in the above, it is desirable that the source side also has the same structure. In the impurity region at the source side, there is formed a region 103a having such a concentration gradient that as the distance from the channel formation region becomes larger, the concentration of the impurity element imparting one conductivity type is increased. Further, in the present specification, in the source side impurity region, a region having an impurity concentration of 1xc3x971020/cm3 or higher is called a source region 103b. 
The present invention is characterized in that the regions 102a and 103a having such concentration gradients are intentionally formed to realize a TFT in which an off current value is considerably low and the ratio of an on current value to the off current value is high. The gate electrode 105 overlaps with the channel formation region 101 and the impurity region 102a through a gate insulating film 104. Note that, in FIG. 1A, reference numeral 100 designates a substrate having an insulating surface; 108, an interlayer insulating film; 109, a source electrode; and 110, a drain electrode. Further, as shown in FIG. 7, a structure may be adopted in which a gate electrode does not overlap with an impurity region.
In a conventional TFT structure, as shown in FIG. 13, there is a boundary due to a definite concentration difference, and the concentration is different like a staircase among a channel formation region 1, a low concentration impurity region 2, and a high concentration impurity region 3. That is, there is a discontinuous concentration distribution. In addition, the concentration in each region is almost constant. Accordingly, in the prior art, since the concentration difference at the boundary between the high concentration impurity region 3 and the low concentration impurity region 2, and the concentration difference at the boundary between the low concentration impurity region 2 and the channel formation region 1 are relatively large, high electric field concentration is generated in the vicinity of each of the boundaries.
Since the off current flows by quantum mechanical effects such as tunneling between bands, it is conceivable that the off current is mainly effected by an electric field. Accordingly, the electric field concentration generated at the boundary causes the off current value of the TFT to increase. Especially, in the conventional TFT structure, there has been a problem in that a high electric field is concentrated by the large concentration difference at the boundary between the channel formation region and the low concentration impurity region.
On the other hand, in the present invention, by providing the impurity region in which the concentration is continuously increased, a definite boundary is eliminated, and the electric field concentration generated in the vicinity of a boundary portion is relieved, so that the TFT structure having a low off current value can be obtained.
In the present invention, as shown in FIG. 1A, although it is most desirable that such a concentration gradient as to completely eliminate a boundary due to a concentration difference of an impurity element in a semiconductor layer is formed in the impurity region 102 (range of 1xc3x971015/cm3 to 1xc3x971021/cm3), the effect of the present invention can also be obtained by lessening the concentration difference between the channel formation region 101 and the impurity region 102a in the vicinity of the channel formation region. Further, the effect of the present invention can also be obtained by lessening the concentration difference at the boundary between the impurity region 102b and the impurity region 102a in the vicinity of the above impurity region.
FIG. 1B shows simulation results in the case where the TFT structure is made one shown in FIG. 1A and is designed to have channel length L=6 xcexcm, channel width W=4 xcexcm, film thickness of the gate insulating film 104=115 nm, film thickness of a polysilicon layer=45 nm, the region 102a (width: 1.5 xcexcm) having a concentration gradient within the range of an impurity concentration (P concentration) of 1xc3x971017/cm3 to 1xc3x971018/cm3, the impurity region 102b having an impurity concentration (P concentration) of 1xc3x971019/cm3, and a carrier concentration (B concentration) of the channel formation region 101=2xc3x971016/cm3. In the simulation results, the vertical axis indicates the intensity of an electric field E (V/cm) of the surface of the semiconductor layer, and the horizontal axis indicates the distance (um) from the channel formation region. A solid line in FIG. 1B shows the state of electric field concentration onto the impurity region of the present invention.
Further, as an example of the prior art, a dotted line in FIG. 1B indicates the state of electric field concentration onto the low concentration impurity region 2 when the concentration distribution in the semiconductor layer of the TFT is made the distribution shown in FIG. 13.
As shown in FIG. 1B, the present invention is provided with at least the impurity region having the concentration gradient within the range of the impurity concentration (P concentration) of 1xc3x971017/cm3 to 1xc3x971018/cm3, so that the electric field intensity of the semiconductor layer surface can be made gentler than the prior art. Therefore, according to the present invention, high electric field concentration is not generated all over the semiconductor layer, and a TFT having a low off current value can be obtained.
The structure of the present invention disclosed in the present specification relates to a semiconductor device including a TFT which includes a gate electrode formed on an insulating surface, an insulating film formed on the gate electrode, and a semiconductor layer formed on the insulating film, characterized in that
the semiconductor layer includes a channel formation region overlapping with the gate electrode, and an impurity region formed to be in contact with the channel formation region, and
the impurity region has a concentration distribution in which as a distance from the channel formation region becomes larger, an impurity concentration is increased.
Further, in the above structure, an impurity element imparting one conductivity type to a semiconductor is phosphorus (P) or arsenic (As), and an n-channel type TFT is obtained. Since this n-channel type TFT has a small off current, it is suitable as a TFT of a pixel portion.
Further, in the above structure, the semiconductor device is characterized in that the impurity region has the concentration distribution in which as the distance from the channel formation region becomes larger, the impurity concentration is continuously increased, and that the impurity region includes at least a region having a concentration gradient of the concentration distribution in a channel length direction.
In the above structures, a semiconductor device includes a first insulating film on the channel formation region, and a second insulating film formed so as to contact with the first insulating film, characterized in that the first insulating film includes a taper portion.
In the above structures, a semiconductor device is characterized in that the taper portion of the first insulating film overlaps with the region having the concentration gradient in the impurity region.
In the above structure, a semiconductor device is characterized in that the second insulating film overlaps with the channel formation region.
In the above structures, a semiconductor device may adopt a structure in which the impurity region overlaps with the gate electrode, and that in which the impurity region does not overlap with the gate electrode.
Further, in the above structure, materials having different etching rates may be suitably selected for the first insulating film and the second insulating film, and for example, the first insulating film may be made a silicon nitride film, and the second insulating film may be made a silicon oxide film.
Further, in the above structures, a semiconductor device is characterized in that the impurity concentration is a concentration of an impurity element imparting one conductivity type to a semiconductor.
Further, in FIG. 1A, in the impurity region, as the distance from the channel formation region becomes larger, the impurity concentration is increased, and the concentration distribution is indicated as a normal distribution. However, the invention is not particularly limited thereto, and the concentration distribution may be an exponential distribution, may be a straight line having a slant, or may be a combination of those.
Conventionally, doping of the impurity element is carried out by using a patterned resist mask, or doping of the impurity element is carried out by using a wiring line as a mask in a self-aligning manner, so that a step-like concentration distribution as shown in FIG. 13 is formed, and the structure of the present invention, that is, the impurity region having the concentration gradient can not be obtained. Further, the present invention is also characterized by a manufacturing method for obtaining the above structure.
In order to achieve the above structure, the structure of the present invention relates to a method of manufacturing a semiconductor device, including the steps of:
forming a gate electrode on an insulating surface;
forming a gate insulating film on the gate electrode;
forming a semiconductor layer on the gate insulating film;
forming an insulating film on the semiconductor layer;
forming an insulating layer having a taper portion on the semiconductor layer by etching the insulating film; and
forming an impurity region in which an impurity concentration is increased toward an end portion of the taper portion, by adding an impurity element imparting one conductivity type to the semiconductor layer through the taper portion.
Conventionally, doping of the impurity element is carried out by using the resist mask formed by using a photomask, and an LDD region, a source region and a drain region are formed. The structure of the above manufacturing method is characterized in that doping is carried out through the taper portion of the insulating layer, and the impurity region having a concentration gradient is formed.
Further, in the above structures, the method of manufacturing a semiconductor device is characterized in that the impurity element imparting one conductivity type is added to the semiconductor layer through the taper portion, and the impurity region where the impurity concentration is increased toward the end portion of the taper portion has at least the concentration gradient within the range of the impurity concentration (P concentration) of 1xc3x971017/cm3 to 1xc3x971018/cm3. Note that, in the present invention, as shown in FIG. 1A, it is most desirable that such concentration gradient as to completely eliminate a boundary due to the concentration difference of the impurity element in the semiconductor layer is formed in the impurity region 102 (range of 1xc3x971015/cm3 to 1xc3x971021/cm3). However, the effect of the present invention can also be obtained by lessening the concentration difference between the channel formation region 101 and the impurity region 102a in the vicinity of the channel formation region. Further, the effect of the present invention can also be obtained by lessening the concentration difference at the boundary between the impurity region 102b and the impurity region 102a in the vicinity of the above impurity region.
Further, a driving circuit and a pixel portion can also be formed on the same substrate.
In order to achieve the above structure, another structure of the present invention relates to a method of manufacturing a semiconductor device, including the steps of:
forming a gate electrode on an insulating surface;
forming a gate insulating film on the gate electrode;
forming a semiconductor layer on the gate insulating film;
forming a first insulating film on the semiconductor layer;
forming a second insulating film on the first insulating film;
forming a resist mask on the second insulating film;
forming a second insulating layer covering a portion which becomes a channel formation region by selectively etching the second insulating film, and forming a first insulating layer having a taper portion on the semiconductor layer by selectively etching the first insulating film;
adding an impurity element imparting one conductivity type to the semiconductor layer while the resist mask is used as a mask; and
forming an impurity region in which an impurity concentration is increased toward an end portion of the taper portion, by adding an impurity element imparting one conductivity type to the semiconductor layer through the taper portion after the resist mask is removed.
The structure of the manufacturing method is characterized in that at the step of forming the resist mask, the resist mask is formed by exposure from a back side of a substrate while the gate electrode is used as a mask.
Further, the structure of the manufacturing method is characterized in that the etching at the step of forming the second insulating layer having the taper portion is a wet etching of a spin system, a dip system or the like.
Further, in the etching at the step of forming the second insulating layer having the taper portion, although it is desirable to form the layer by one etching step since the number of steps can be reduced, it may be formed by plural etching steps. Further, the second insulating layer may be formed by a dry etching. Further, the second insulating layer may be formed by a combination of the wet etching and the dry etching.